1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell to prevent closure of the difference of the programmed threshold voltage and the erase threshold voltage of the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1a illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a p-type substrate 12. An n+ drain region 14 and an n+ source region 16 are formed within the p-type substrate 12.
A relatively thin gate dielectric 36 is deposited on the surface of the p-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A p+ diffusion 18 is placed in the p-type substrate 12 to provide a low resistance path from a terminal 20 to the p-type substrate. The terminal 20 will be attached to a substrate voltage generator Vsub. In most application of an EEPROM, the substrate voltage generator Vsub is set to the ground reference potential (0V).
The source region 16 is connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V).
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process, some of the hot electrons will be trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the p-type substrate 12. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
To erase the flash EEPROM cell 10 as described in U.S. Pat. No. 5,481,494(Tang et al.), as shown in FIG. 2a, a moderately high positive voltage (on the order of 5V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of xe2x88x9210V). The substrate voltage generator VS are set to the ground reference potential. The drain voltage generator VD is usually disconnected from the terminal 24 to allow the drain region 14 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 16. The electrons are then extracted to the source region 16 by the Fowler-Nordheim tunneling.
Further Tang et al. shows a method for tightening the threshold voltage VT distribution of an array of flash EEPROM cells. The moderately high positive voltage (5V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
Referring back to FIG. 1a during the erasure process, as a result of band to band tunneling, some positive charges or xe2x80x9chot holesxe2x80x9d 38 will be forced and trapped in the tunneling oxide 36. These trapped positive charges or xe2x80x9chot holesxe2x80x9d 38 will cause the threshold voltage of the programmed flash EEPROM cell 10 to decrease. As can be shown in FIG. 2e, after repeatedly performing write/erase cycling, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time, the flash EEPROM will no longer be able to operate reliably to store digital data.
FIG. 1b illustrates an alternate cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a P-type substrate 12. An N-type material is implanted within the P-type substrate 12 to a lightly doped concentration to for the N-well 47. Within the N-well 47, a P-type material is implanted to a lightly doped concentration to form the P-well 45. An N+ drain region 14 and an N30  source region 16 are formed within the P-type well 45.
A relatively thin gate dielectric 36 is deposited on the surface of the P-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A P+ diffusion 18 is placed in the P-type substrate 12 to provide a low resistance path from a terminal 20 to the P-type substrate. The terminal 20 will be attached to a substrate voltage generator VSub. In most application of an EEPROM, the substrate voltage generator VSub will be set to the ground reference potential (0V).
The source region 16 will be connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD. The P-well 45 is connected to a P-well voltage generator VPw through terminal 44. The N-well 47 is connected to the N-well voltage generator VNw through the terminal 46.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high positive voltage (on the order of 10V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS and the P-well voltage generator VPw are set to the ground reference potential (0V). The N-well voltage generator VNw is disconnected from the terminal 46 to allow the N-well 47 to float.
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process, some of the hot electrons will be trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the P-type substrate 12. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
U.S. Pat. No. 5,481,494 (Tang et al. 494), U.S. Pat. No. 5,485,423 (Tang et al. 423), U.S. Pat. No. 5,412,608 Oyama), U.S. Pat. No. 5,414,669 (Tedrow et al.), U.S. Pat. No. 5,790,460 (Chen et al.), U.S. Pat. No. 5,416,738 (Shrivasta), U.S. Pat. No. 5,546,340 (Hu et al.), and U.S. Pat. No. 5,781,477 (Rinerson et al.) each describe a form of erasing a flash EEPROM conventionally referred to as Negative Gate Erase. To erase the flash EEPROM cell 10 using Negative Gate Erase, as shown in FIG. 2b, a moderately high positive voltage (on the order of 5V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of xe2x88x9210V). The substrate voltage generator VSub and the P-well voltage generator VPw are set to the ground reference potential. The drain voltage generator VD and the N-well voltage generator VNw are respectively usually disconnected from the terminal 24 to allow the drain region 14 to float from the terminal 44 to allow the N-well 47 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 16. The electrons are then extracted to the source region 16 by the Fowler-Nordheim tunneling.
Referring back to FIG. 1b, during the erasure process, because of band to band tunneling, some positive charges or xe2x80x9chot holesxe2x80x9d 38 are forced into the tunneling oxide 36 and trapped there in the tunneling oxide 36. Further, defects 40 at the interface of the tunneling oxide 36 and the P-well 45 will create trapped positive charges. These trapped positive charges or xe2x80x9chot holesxe2x80x9d 38 and the interface traps 40 will cause the threshold voltage of the programmed flash EEPROM cell 10 to decrease. As can be shown in FIG. 2c, after repeatedly performing write/erase cycling, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time, the flash EEPROM will operate less reliably to store digital data.
Further Tang et al. 494 shows a method for tightening the threshold voltage VT distribution of an array of flash EEPROM cells. The moderately high positive voltage (5V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
A variant of the negative gate erase is the positive gate erase discussed in U.S. Pat. No. 5,760,605 (Go). In Go the control gate is brought to a voltage level of approximately +11.0V and the source is brought to the ground reference potential. These biasing conditions allow a net negative potential to be xe2x80x9cstoredxe2x80x9d on the floating gate to establish the xe2x80x9cerasedxe2x80x9d condition. For programming of the flash EEPROM cell the control gate is brought to the ground reference potential, the drain is brought to a voltage of approximately +13.0V and the source is brought to approximately +11.0V. A net positive potential is thus xe2x80x9cstoredxe2x80x9d on the floating gate to establish the xe2x80x9cprogrammedxe2x80x9d condition.
Oyama and Hu et al. further discuss techniques for equalization of the threshold voltage VT after erase or correction of over erase conditions.
U.S. Pat. No. 5,596,528 (Kaya et al.), U.S. Pat. No. 5,491,657 (Haddad et al.), U.S. Pat. No. 5,357,476 (Ku et al.), U.S. Pat. No. 5,598,369 (Chen et al.), U.S. Pat. No. 5,581,502 (Richert et al.), U.S. Pat. No. 5,726,933 (Lee et al. 933) and Hu et al. each describe a form of erasing the flash EEPROM cell 10 conventionally referred to as a Source Erase. To erase the flash EEPROM cell 10 using Source Erase, as shown in FIG. 3a, a relatively high positive voltage (on the order of +10.0V) is generated by the source voltage generator Vs. The control gate voltage generator VG, the P-well voltage generator VPw, and the substrate voltage generator VSub are each set to the ground reference potential. The drain voltage generator VD and the N-well voltage generator VNw are generally disconnected respectively form the drain region 14 and the N-well 47 to allow the drain region 14 and the N-well 47 to be floating. Under these biasing conditions there is similarly a large electric field is developed across the tunneling oxide 36 the source region 16. This electric field causes the electrons 31 trapped in the floating gate 32 to be extracted to the source region 16 by the Fowler-Nordheim tunneling.
FIG. 3b shows the threshold voltage VT versus the number of repeated program/erase cycles of the flash EEPROM. As described above, the xe2x80x9chot holesxe2x80x9d 38 and the interface traps 40 of FIG. 1 create positive charges that raise the threshold voltage VT of the flash EEPROM cell. The combination of the decrease 62 in the programmed threshold 60 and the increase 67 of the erased threshold voltage 65 causes the separation of the programmed threshold voltage 60 and the erase threshold voltage 65 to close until the flash EEPROM cell fails. At this time, the flash EEPROM cell will no longer be able to retain the digital data reliably.
U.S. Pat. No. 5,231,602 (Radjy et al.) describes a method of erasing a flash EEPROM cell by controlling the electric field across the tunneling oxide. The drain is connected through a variable resistor to a programming voltage source and a variable voltage source is connected to the source. The variable voltage source is adjusted between 0 and 5V, while the programming voltage source is set between 5V and 20V. The tunneling. current is optimized by adjustment of the variable resistor and the variable voltage.
A third method of erasure of a flash EEPROM cell is described in U.S. Pat. No. 5,521,866 (Akaogi) and is termed a Channel Erase. Channel Erase, as shown in FIG. 4a, has the control gate voltage generator VG set to a relatively large negative voltage (xe2x88x9210.0V) to place the control gate 28 at the relatively large negative voltage. The P-well voltage generator VPw is set to a moderately high voltage (+5.0V) to set the P-well 45 to the moderately high voltage.
The source 16, the drain 14, and the N-well are respectively disconnected from the source voltage generator Vs, the drain voltage generator VD, and the N-well voltage generator VNw to cause the source 16, the drain 14, and the N-well to be floating. The substrate voltage generator VSub is set to the ground reference potential so that the substrate is biased to the ground reference potential.
FIG. 4b illustrates the degradation of the programmed threshold voltage 70 and the erased threshold voltage 75 as the cumulative number of program/erase cycles of the flash EEPROM is increased. In the Channel Erase, the negative charges 31 are extracted across the surface of the floating gate 32 through the tunneling oxide 36 to the P-well 45. Some of these charges will be trapped in the tunneling oxide 36. As the number of program/erase cycles is increase, the programmed threshold voltage 70 begins to decrease 72, while the erased threshold voltage 75 increases modestly 77. This indicates that eventually the difference between the programmed threshold voltage 70 and the erased threshold voltage 75 will eventually decrease until the flash EEPROM cell 10 can no longer retain digital data reliably.
Tang et al. 423 as shown in FIG. 5, describes a method of erasure of a flash EEPROM. A moderately large positive voltage pulse (+5.0V) is generated by the source voltage generator VS. Simultaneously, a negative ramp voltage is developed by the gate control voltage generator VG. The negative ramp voltage has a first incremental voltage of approximately xe2x88x925.0V and each of the following increments is xe2x88x920.9V. The maximum voltage generated by the gate control voltage generator VG is approximately xe2x88x929.5V. The drain voltage generator VG will be disconnected from the drain to allow the drain to float and the substrate voltage generator will be set to the ground reference potential as above described. This method will achieve an averaging of the tunneling field during the entire erase cycle.
U.S. Pat. No. 5,949,717 (Ho et al.), assigned to the Same Assignee as the present invention, and xe2x80x9cUsing Erase Self-Detrapped Effect To Eliminate the Flash Cell Program/Erase Cycling Vth Window Closexe2x80x9d Lee, et al., Proceedings 37th Annual IEEE International Reliability Symposium, IEEE, March 1999, pp. 24-29, describes, what is termed, a source erase followed by a channel erase. Referring to FIGS. 1a and 6a, the initial period of the erase cycle (phase 1) or erasure phase 650 starts by setting the gate control voltage generator VG 26 and thus the control gate to the ground reference potential (0V) 652. The source voltage generator VS 22 and consequently the source region 18 will be set to a relatively high voltage (approximately 10V) 654. The substrate voltage generator Vsub 20 and thus the p-type substrate 2 will be set to the ground reference potential (0V) 656. The drain voltage generator VD 24 will be disconnected from the drain region 14 to be floating 658. The voltages as described will force the trapped charges on the floating gate 30 of the flash EEPROM cell 10 to migrate to the end of the floating gate 30 immediately above the source region 18. The electric field in the tunnel oxide 36 will force these trapped electrons to flow through the tunnel oxide 36 by the Fowler-Nordheim tunneling into the source region 18. At the completion of the phase 1650 there will be positive charges 38 remaining in the tunnel oxide 36 as described above. Additionally there will be electrons 42 that have been trapped in the tunnel oxide 36 and at the surface states 40, again as described above.
A second phase (phase 2) 660 will terminate the erase cycle by bringing the source voltage generator VS 22 to the ground reference potential (0V). The gate control voltage generator VG 26 and the substrate voltage generator Vsub 20 will remain at the ground reference potential (0V) 662 and 666. The drain voltage generator VD 24 will remain disconnected from the drain region 24 to keep the drain region 24 floating 668.
Having terminated the erasure phase 650 in phase 2660, the detrapping phase (phase 3) can begin. The gate control voltage generator VG 26 is brought to a relatively large negative voltage (xe2x88x9210V) 672. Concurrently, the source voltage generator VS 22 is disconnected from the source region 18 to allow the source region 18 to float 674. Also concurrently, the substrate voltage generator Vsub 20 and thus the p-type substrate 2 will be brought to a moderately large positive voltage (+5V) 676. At this time the drain voltage generator VD 24 will remain disconnected from the drain region 14 thus maintaining the drain region 14 at a floating condition 678.
The range of the source voltage generator VS 22 will be from 5.0V to 15V. The range of the gate control voltage generator VG 26 is from xe2x88x925.0V to xe2x88x9215.0, and the range of the substrate voltage generator Vsub 20 is from 0.5V to the value of the power supply voltage source or about 5.0V.
The relative period of time x for the phase 1650, of the erase cycle is 50 msec. in duration but can range from 10 msec. to 100 msec. Phase 2660 and Phase 3670 have periods of time y and z are approximately 30 and 50 msec. in duration respectively. The range in duration z of phase 3670 is from 10 msec. to 100 msec. Additionally the phase 3670 would normally be practiced at every erase cycle. However, the phase 3670 could be practiced periodically to eliminate trapped charges.
Referring to FIG. 6b, the programmed threshold voltage 80 will remain at a relatively constant value of approximately 6V for at least 100,000 program/erase cycles. Also, as can be seen, the erased threshold voltage 85 will remain at a constant value of approximately 0.5V for the 100,000 program/erase cycles. By not degrading the threshold as seen in FIG. 2c, the flash EEPROM cell 10 of FIG. 1a will maintain operation without failure for program/erase cycle in excess of 100,000 cycles.
Further, the March 1999 IEEE Reliability Symposium Paper by Lee, et al. describes, what is termed, a negative gate erase followed by a channel erase. Referring to FIGS. 1a and 7a, the initial period of the erase cycle (phase 1) or erasure phase 750 starts by setting the gate control voltage generator VG 26 and thus the control gate to a relatively large negative voltage (xe2x88x9210V) 752. The source voltage generator VS 22 and consequently the source region 18 will be set to a moderately high voltage (approximately 4.3V) 754. The substrate voltage generator Vsub 20 and thus the p-type substrate 12 will be set to the ground reference potential (0V) 756. The drain voltage generator VD 24 will be disconnected from the drain region 14 to be floating 758. The voltages as described will force the trapped charges on the floating gate 30 of the flash EEPROM cell 10 to migrate to the end of the floating gate 30 immediately above the source region 18. The electric field in the tunnel oxide 36 will force these trapped electrons to flow through the tunnel oxide 36 by the Fowler-Nordheim tunneling into the source region 18. At the completion of the phase 1750 there will be positive charges 38 remaining in the tunnel oxide 36 as described above. Additionally there will be electrons 42 that have been trapped in the tunnel oxide 36 and at the surface states 40, again as described above.
A second phase (phase 2) 760 will terminate the erase cycle by bringing the source voltage generator VS 22 to the ground reference potential (0V) 764. The gate control voltage generator VG 26 will remain at the relatively large negative voltage (xe2x88x9210V) 762. The substrate voltage generator Vsub 20 will remain at the ground reference potential (0V) 766. The drain voltage generator VD 24 will remain disconnected from the drain region 24 to keep the drain region 24 floating 768.
Having terminated the erasure phase 750 in phase 2760, the detrapping phase (phase 3) 770 can begin. The gate control voltage generator VG 26 remains at the relatively large negative voltage (xe2x88x9210V) 772. Concurrently, the source voltage generator VS 2220 will remain at the ground reference potential (0V) 774. Also concurrently, the substrate voltage generator Vsub 20 and thus the p-type substrate 12 will be brought to a moderately large positive voltage (+5V) 776. At this time the drain voltage generator VD 24 will remain disconnected from the drain region 14 thus maintaining the drain region 14 at a floating condition 778.
The range of the source voltage generator VS 22 will be from 0V to 10V preferably 4.3V. The range of the gate control voltage generator VG 26 is from xe2x88x925.0V to xe2x88x9215.0, preferably xe2x88x9210.0V, and the range of the substrate voltage generator Vsub 20 is from 0.5V to the value of the power supply voltage source or about 5.0V.
The relative period of time x for the phase 1750, of the erase cycle is 50 msec. in duration but can range from 10 msec. to 100 msec. Phase 2760 and Phase 3770 have time periods y and z are approximately 30 and 50 msec. in duration respectively. The range in duration z of phase 3770 is from 10 msec. to 100 msec. Additionally the phase 3770. would normally be practiced at every erase cycle. However, the phase 3770 could be practiced periodically to eliminate trapped charges.
Referring to FIG. 7b, the programmed threshold voltage 90 will remain at a relatively constant value of approximately 6V for at least 100,000 program/erase cycles. Also, as can be seen, the erased threshold voltage 95 will remain at a constant value of approximately 0.5V for the 100,000 program/erase cycles. By not degrading the threshold as seen in FIG. 2c, the flash EEPROM cell 10 of FIG. 1a will maintain operation without failure for program/erase cycle in excess of 100,000 cycles.
The remaining related patent applications, included herein by reference, illustrate methods to improve the difference in the programmed threshold voltage and the erased threshold voltage by dual phase erasing methods eliminating charges from the floating gate and detrapping the charges from the tunneling oxide of the flash EEPROM cell.
An object of this invention is to provide a method for the erasure of data from a flash EEPROM.
Another object of this invention is to provide a method to eliminate electrical charges trapped in the tunneling oxide and within surface states at the interface of the semiconductor substrate.
Further an other object of this invention is to eliminate electrical charges trapped in the tunneling oxide of a flash EEPROM to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles.
To accomplish these and other objects a first embodiment of a combination method to erase a flash EEPROM cell begins by negative gate erasing the flash EEPROM to remove charges from the floating gate. The negative gate erasing begins by first applying a first relatively large negative voltage pulse to the control gate of the flash EEPROM. The first relatively large negative voltage pulse has a voltage of from approximately xe2x88x925.0V to approximately xe2x88x9215.0V, preferably xe2x88x9210.0V.
Concurrently a first moderately large positive voltage pulse is applied to the source. The first moderately large positive voltage pulse has a voltage of from approximately +0.5V to approximately +5.0V, preferably +4.3V.
Also, concurrently a ground reference potential is applied to the first well and the semiconductor substrate, and the drain and second well are disconnected to allow the drain and second well to float.
At the completion of the negative gate erasing, the flash EEPROM cell is then source erased to further remove charges from the floating gate. The source erase procedure begins by floating the drain and the second well and concurrently applying the ground reference potential to the semiconductor substrate, the drain, and the first well. Simultaneously, a relatively large positive voltage pulse is applied to the source. The relatively large positive voltage pulse as a voltage of from approximately +5.0V to approximately +15.0V, preferably 10.0V.
Upon completion of the source erasing, the flash EEPROM is then channel erased to detrap charges from the tunneling oxide. The channel erase begins by applying a second relatively large negative voltage pulse to the control gate of the EEPROM cell and concurrently applying a second moderately large positive voltage pulse to the first well. The second relatively large negative voltage pulse has a voltage of from approximately xe2x88x925.0V to approximately xe2x88x9215.0V, preferably xe2x88x9210.0V and the second moderately large positive voltage pulse has a voltage of from approximately +0.5V to approximately +5.0V, preferably +5.0V.
At this same time, a ground reference potential is applied to the semiconductor substrate and the drain, the source, and the second well are floated.
The detrapping the flash EEPROM allows a separation of a programmed threshold voltage from an erased threshold voltage to be maintained over the repeated writing and erasing of the flash EEPROM, thus improving the program/erase threshold voltage closure.
The first moderately large positive voltage pulse, the second moderately large positive voltage pulse, the first relatively large negative voltage pulse, relatively large positive voltage pulse, and the second relatively large negative voltage pulse each have a duration of approximately 10 m second to two seconds.
The duration of the second moderately large positive pulse and the second relatively large negative pulse will prevent degradation to the tunneling oxide during the source erasing due to a lesser electric field in the tunneling oxide.
A second embodiment of a combination method to erase a flash EEPROM cell begins by negative gate erasing the flash EEPROM to detrap said flash EEPROM cell. The negative gate erasing begins by floating said drain. Concurrently the ground reference potential is applied to the semiconductor substrate. Concurrently, a voltage potential in decreasing step wise increments from a ground reference potential to a first relatively large negative voltage level is applied to said control gate. Also, concurrently a voltage potential in increasing step wise increments from the ground reference potential to a moderately large positive voltage level is applied to said source.
The final step of the method of the second embodiment is source erasing said flash EEPROM cell. The source erasing begins by continuing to maintain the first relatively large negative voltage level to the control gate of said EEPROM cell. At this same time a moderately large positive voltage pulse is applied to said semiconductor substrate. During the source erasing the drain and source are floating.
The negative gate erasing the flash EEPROM removes charges from the floating gate, while the source erasing detraps the flash EEPROM to removes charges trapped in the tunneling oxide between the floating gate and the semiconductor substrate. The combination of the negative gate erasing followed by the source erasing of the EEPROM cell allows a separation of a programmed threshold voltage from an erased threshold voltage to be maintained over the repeated writing and erasing of said flash EEPROM, thus improving said write/erase threshold voltage closure.
The moderately large positive voltage level has a voltage range of from approximately 0.5V to approximately 5V, preferably 4.3V. The moderately large positive voltage level has a first initial voltage increment that ranges from approximately 1 mV to approximately 1.0V. The moderately large positive voltage level has a first plurality of subsequent voltage increments that ranges from approximately 1 mV to approximately 1.0V. The first initial voltage increment and the first plurality of subsequent voltage increments have a time duration that ranges from approximately 1 m second to approximately 10 seconds.
The relatively large negative voltage level has a voltage range of from approximately xe2x88x925V to approximately xe2x88x9215V, preferably xe2x88x9210V. The relatively large negative voltage level has a second initial voltage increment that ranges from approximately xe2x88x921 mV to approximately xe2x88x921.0V. The relatively large negative voltage level has a second plurality of subsequent voltage increments that range from approximately xe2x88x921 mV to approximately xe2x88x921.0V. The second initial voltage increment and the second plurality of subsequent voltage increments have a time duration that ranges from approximately 1 m second to approximately 10 seconds.
The moderately large positive voltage pulse has a voltage level that is preferably 5.0V but has a voltage range of from approximately 0.5V to the voltage level that is approximately that of the power supply voltage source.
The duration of the negative gate erasing and the source erasing each range from approximately 10 m seconds to approximately 100 m seconds.
A third embodiment of a combination method to erase a flash EEPROM cell begins by source erasing said flash EEPROM cell. The source erasing begins by applying a voltage level in increasing step wise increments from the ground reference potential to apply a relatively large positive voltage level to the source of said EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate, while the drain is floating. The second step of the combination method to erase the flash EEPROM cell is channel erasing. Channel erasing begins by floating said source and drain. A moderately high positive voltage pulse is applied to said semiconductor substrate, while simultaneously applying a relatively large negative voltage pulse to said control gate.
The source erasing the flash EEPROM removes charges from the floating gate, while the channel erasing the flash EEPROM removes charges trapped in the tunnel oxide between the floating gate and the semiconductor substrate.
The source erasing followed by the negative gate erasing the flash EEPROM allows a separation of a programmed threshold voltage from an erased threshold voltage to be maintained over the repeated writing and erasing of said flash EEPROM, thus improving said write/erase threshold voltage closure.
The relatively high voltage has a voltage of from approximately 5.0V to approximately 10.0V. The moderately high voltage pulse has a voltage of from approximately 0.5V to approximately 5.0V. And the relatively large negative voltage pulse has a voltage of from approximately xe2x88x925.0V to approximately 15.0V.
The relatively high voltage level, the moderately high voltage pulse, and the relatively large negative voltage pulse each have a duration of from approximately 10 m seconds to approximately 100 m seconds.